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62508hkim / 52808hkim b8-9279 no.a1187-1/20 LC749460W overview the LC749460W is rgb processor lsi whic h converts the interlace tv signal such as ntsc or pal into progressive signal, optimizes and adjusts the image quality of these tv si gnals to the fpd devices such as lcd-tv, and output the signal that converts the resolution according to the connected panel. it optimizes lsi for the pixel display device which deals with image quality and high resolution image. a vide o signal processing system for flat panel display can be formatted easily by combining with microcomputer and lcd panel. features (1) analog input ? built-in 4ch a/d converter ? cvbs 2ch, s-video, yc bcr/ypbpr input (supports 480 i/576i, 480p/576p, 1080i, 720p) 2ch (2) digital input/output ? support digital video input: ycbcr 24-bit or ycbcr 16-bit (4:2:2) signal or itu-r bt656 (8-bit) input ? support dtv (480i/576i, 480p/576p, 1080i, 720p) input: ycbcr/ypbpr/rgb digital 24-bit signal input ? digital rgb 30-bit (24-bit)/ycbcr 30-bit (24-bit) signal output (3) yc separation video decoder (ntsc, pal, secam) ? adaptive 3d yc separation (ntsc)/adap tive 3 or 5 line yc separation (pal). ? digital agc. digital acc (4) de-interlacing ? motion adaptive jaggy-less de-interlacing ? 2:3 pull-down, 2:2 pull-down continued on next page. ordering number : ena1187a cmos ic silicon gate digital rgb processor lsi specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. : sanyo digital picture improvement core
LC749460W no.a1187-2/20 continued from preceding page. (5) resolution conversion ? resolution conversion (to wxga) ? pip/pop. (6) picture quality improvement ? noise reduction (3d nr) ? cross color/cross luminance canceller ? horizontal edge correction ( lti/cti), sharpness (horizonta l/vertical), shadow adjuster ? white/black stretch. flesh tone improvement. ? hue/color gain adjustment/color exciter (6 phase rgbymc independent saturation correction). ? brightness/contrast adjustment. white balance/black balance adjustment. ? correction (rgb independent, lut system programm able). dithering (10-bit/8-bit). clamp control. ? clock generator (pll)/various of built-in interface (sdram if, i 2 c bus, 3 wire-bus) ? yuv to rgb conversion/ycbcr to rgb conversion/ypbpr to rgb conversion/rgb to ycbcr conversion lsi specifications ? supply voltage core: 1.2v, i/o block: 3.3v ? maximum operating frequency: 85mhz ? package: lqfp256 principal applications ? lcd tvs, monitors, and projectors, pdp tvs, progressive scan tvs, and projection tvs 1. input 1-1 input signal format (digital input) digital data port supports the following signal input formats. 24bit (4:4:4) ycbcr/rgb: ntsc/pal (480i/576i), 480p, 576p, hd (1080i/720p) 16bit (4:2:2) ycbcr: ntsc/pal (480i/576i), 480p, 576p, hd (1080i/720p) 8bit based on itu-r bt656system (h/v sync input is needed): ntsc/pal (480i/576i) digital 2 system input such as 16bit (4:2:2) ycbcr + 8bit (itu-r bt656), 8bit (itu-r bt656) + 8bit (itu-r bt656) are possible 1-2 input signal format (analog input) analog port can be connected to all of the following input. cvbs 2ch: composite input 2ch s-video: s video input 1ch ypbpr input (supports 480i/576i, 480p/576p, 1080i, 720p input): component input 2 system 2. digital video decoder block this lsi carries video decoder which converts the video signal of ntsc, pal and secam or component video signal into digital picture signal. it decodes digital picture data by inputting the video signals of ntsc, pal and secam which are converted from analog to digital. it supports composite video signal, s video signal and component signal (480i). 3. de-interlacing block when inputting ntsc (480i) and pal (576i), it can implement motion adaptive de-interlacing, cinema mode de-interlace, 3d noise reduction and cro ss color/cross luminance canceller. at 4 80p, 576p, 1080i, 72 0p, this block is set to the through state. 3-1. motion adaptive de-interlacing at de-interlacing block, it operates the movement detectio n to every pixel that inputted. as a result, it does interpolation between front and back field to the pixel that judged as static, and does interpolation inside field to the pixel that judged as move. so de-interlacing can be done. in that case, as for interpolation in between field of move part, it is possible to produce less notched (less-jaggy) and smooth image because of interpolation that considers the correlation of oblique direction.
LC749460W no.a1187-3/20 3-2. cinema mode de-interlacing (3-2/2-2 pull-down) when ntsc/pal interlace signal generated from film (cin ema) source or 30p source such as cartoon are inputted, it does auto-discr iminate cinema/30p source and cinema mode de-interlace that suitable for source. 3-3. 3d noise reduction this has built-in round type 3d noise reduction function that decreases the noise between frames. in this block luminance signal and color difference signal can be processed independently. 3-4. cross color/cross luminance canceller this function can decrease the cross color, noise and cross luminance which are generated when ntsc input signal from composite terminal. by using this function, it can produce vivid image without color blotting and dot interruption. 4. scaler block it implement the up/down scaling of the various input signal of analog and digital that fixed to xga, wxga of output resolution. full/panorama/zoom display is possible and maximum resolution is wxga (1366 768 and 85mhz pixel clock). additionally, this has built-in 2scaler sy stem and enable to display 2screen such as pop/pip. 5. image quality adjustment block this has various image quality blocks and enables to implement the image quality adjustment to fix with flat panel tv. 5-1. horizontal edge correction (lti/cti) lti/cti does edge correction of input signal. it improves the sharpness of image by making the transients of input signal steep. in this case, it is possible to make natural image because there is no peak such as overshoot and undershoot attached at the edge part of image. this function operates independently luminance signal and color difference signal. 5-2. sharpness (horizontal/vertical) sharpness can do edge correction of input signal. in this function, unlike the above function, the moderate peak is added around edge correction. in this case, coring which emphasizes neither an amount of peak nor slight noise can be controlled by register. this function is operated only for luminance signal. 5-3. shadow adjuster shadow adjuster add the moderate peak at front and back of detected edge of input signal and with added shadow of image, so it can produce sharpness image. 5-4.white/black stretch as far as white-black stretch is concerned, it stretches the level of white side and black side of y signal of ycbcr signal according to white-black p eak inside picture of just before fi eld, apl (average picture level) of luminance, distribution information and microcomputer setting information. white and black peak are the max value and min value of input data in 1 field. when using white/black stretch, each setting value should be set properly. 5-5. flesh color correction flesh color correction can extract flesh color and adjust the fresh color without influencing other colors. 5-6. color phase/color gain adjustment the phase adjustment can adjust the hu e on entire screen. the color gain ad justment can adjust the density of colors by controlling the gain of color phase signal. this function can adjust independently by cb and cr. 5-7. color exciter color exciter can control the gain of chroma in red, green, blue, magenta, yellow, cyan respectively. 5-8. brightness/contrast brightness can adjust the brightness of entire screen, and contrast can adjust gain of brightness. 5-9. white balance/black balance adjustment this function can do white adjustment and black adjustment of lcd panel. 5-10. gamma correction it is possible to make the optional gamma curve that fix to lcd panel characteristic. it is also possible to adjust r, g and b independently by writing the adjustment value in lut inside lsi 5-11. dither when the signal processing of internal 10/12bit is output by 8/10bits, the dither rounds the 2/4bits of lsb and output it.
LC749460W no.a1187-4/20 6. built-in osd block this function can do osd (on screen display) on the image data after adjusting image quality. the amount of the expression per pixel can be selected from 16 indexes (4 bits: clut4) and 256 indexes (8 bits: clut8). the color pallet of the index can set alfa 4-bit of blending coefficient and 8-bit of green, blue, and the red. displayed character and icon, etc. need to set the gbr color to the color pallet and transmit the bmp data in the state of clut 4/8. the drawing engine is built-in, besides, it is possible not only to draw the transmitted bmp data to sdram but also do the rectangle drawing (including point and line drawing) and copy inside sdram. 7. output/i/f/others 7-1. matrix conversion the following matrix conversion is possible for 2 sy stems after digital and analog input are selected. ycbcr to rgb ypbpr to rgb ypbpr to ycbcr rgb to ycbcr 7-2. output format output is possible with the following format. digital rgb (30-bit/24-bit) digital ycbcr (30-bit/24-bit) 7-3. clamp control this can generate clamp signal in external lsi or in the built-in ad converter. in addition, it can generate optional pulse(?h?, ?l?, ?hi-z?) by comparing to the threshold value in the inside the lsi. 7-4. sdram interface this built-in sdram interface, the system can be made up easily by connecting 64mbits sdram (512word 32bit 4bank) 1 piece or 128mbits sdram (1024word 32bit 4bank) 1 piece in directly. in this case, more than?- 60? speed grade of sdram is recommended. 7-5. external osd interface this allows the interface with external osd microcomputer using input pin 41 to 45 and output pin 36 to 38. it can display closed caption and teletext data. 7-6. i 2 c interface/3 wire bus interface it basically controls the internal register using i 2 c interface. the slave address can be a switch by controlling pin53 (i 2 c sel) according to the system. the slave address is as follows. i 2 csel ?l? ?0111000+(r/w)? i 2 csel ?h? ?0111001+(r/w)? a part of register can be contro lled by 3wire bus interface as well.
LC749460W no.a1187-5/20 i/o specifications 1. input signals the kinds of signals the number of pins pin symbol explanation remarks 1 cvbs1 ntsc/pal input 1 1 cvbs2 ntsc/pal input 2 1 asyin s-video input y 1 ascin s-video input c 1 ayin1 component input y1 1 acbin1 component input cb1 1 acrin1 component input cr1 1 ayin2 component input y2 1 acbin2 component input cb2 1 acrin2 analog video signal component input cr2 8 ygi y or g or sy input 8 cbi cb or b or yc input video signal 8 cri digital video signal cr or r or itu-r bt656 input 1 hs1i horizontal sync signal horizontal sync signal for digital input 1 1 vs1i vertical sync signal vertical sync signal for digital input 1 1 hs2i horizontal sync signal horizontal sync signal for digital input 2 1 vs2i vertical sync signal vertical sync signal for digital input 2 1 shsi horizontal sync signal horizontal sync signal for analog input sync signal 1 svsi vertical sync signal vert ical sync signal for analog input 1 he1i data enable data enable (horizontal/composite) for digital input 1 data enable signal 1 ve1i vertical data enable data enable (vertical) for digital input 1 1 fld1i field field signal input for digital input 1 field signal 1 fld2i field field signal input for digital input 2 1 osdg external osd signal g 1 osdb external osd signal b 1 osdr external osd signal r 1 osden external osd enable osd signal 1 osdal external osd blending enable 1 ck1i pixel clock pixel clock input for digital input 1 1 ck2i pixel clock pixel clock input for digital input 2 1 xtal1 system clock fixed clock input 1 pixel clock fixled oscillation 1 xtal2 system clock fixed clock input 2 system reset 1 xrst system rese t system reset input negative-logic total 56 - - - 2. output signal the kinds of signals the number of pins pin symbol explanation remarks 10 ygo 10 cbo 10 cro digital video signal rgb/ycbcr output dithered 8bit output is possible. video signal 1 svo analog video signal monitor output 1 hso horizontal sync signal sync signal 1 vso vertical sync signal data enable signal 1 deo data enable field signal 1 fldo field field out put or vertical data enable output pixel clock 1 cko pixel clock 1 osdho external osd horizontal sync signal 1 osdvo external osd vertical sync signal osd signal 1 osdcko external osd pixel clock continued on next page.
LC749460W no.a1187-6/20 continued from preceding page. the kinds of signals the number of pins pin symbol explanation remarks clamp pulse 1 clpp clamp pulse for external adc pulse output to check ad clamp period 1 clpcvbs1 clamp level for cvbs1 1 clpcvbs2 clamp level for cvbs2 1 clpsy clamp level for sy 1 clpsc clamp level for sc 1 clpy1 clamp level for y1 1 clpcb1 clamp level for cb1 1 clpcr1 clamp level for cr1 1 clpy2 clamp level for y2 1 clpcb2 clamp level for cb2 clamp level 1 clpcr2 clamp level for cr2 clamp level discriminator output (large: l, small: h, coincident: hi-z) pwm output 1 pwmo pwm charge pump output 1 chpmpdo charge pump for built-in pll total 52 - - - 3. control signal the kinds of signals the number of pins pin symbol explanation remarks 1 sda i 2 c data 1 scl i 2 c clock i 2 c bus 1 i 2 csel i 2 c slave address switch low: ?0111000+(r/w)? high: ?0111001+(r/w)? normally ?l? 1 aida 3-wire bus data input/output 1 aics 3-wire bus chip select 3-wire bus 1 aick 3-wire bus clock total 6 - - - 4. sdram control signal the kinds of signals the number of pins pin symbol explanation remarks 1 sdcki clock input clock 1 sdcko clock output 1 sdras row address strobe signal output 1 sdcas column address strobe signal output control system signal 1 sdwe write enable signal output 11 sdad address signal output address system 4 sdbs bank select signal output 4 sddqm sdram data mask signal output data system 32 sddq data input/output total 56 - - - 5. other signals the kinds of signals the number of pins pin symbol explanation remarks 1 scanmd scan test g enerally fixed as ?l? scan test 1 scanen scan test g enerally fixed as ?l? test 2 test test setting generally fixed as ?l? 4 vrt 4 vrb reference input for adc 4 dacrefp adc/afe 4 dacrefm reference output for adc total 20 - - -
LC749460W no.a1187-7/20 package dimensions unit : mm (typ) 3365 sanyo : lqfp256k(28x28) 30.0 28.0 30.0 28.0 0.5 0.1 (1.4) (1.4) 0.4 1.6 max 0.16 0.125 1 256
LC749460W no.a1187-8/20 pin assignment sddq14 sddq15 sddq7 sddq6 dv ss 33 dv dd 33 sddq5 sddq4 sddq3 sddq2 sddq1 sddq0 dv ss 33 dv dd 33 dv ss 12 dv dd 12 pwmo fldo/veo deo/heo cko hso vso cro0 cro1 cro2 cro3 cro4 dv ss 33 dv dd 33 cro5 cro6 cro7 cro8 cro9 cbo0 cbo1 cbo2 cbo3 cbo4 cbo5 cbo6 cbo7 dv ss 33 dv dd 33 dv ss 12 dv dd 12 cbo8 cbo9 ygo0 ygo1 ygo2 ygo3 ygo4 ygo5 ygo6 ygo7 ygo8 ygo9 xrst dv ss 33 dv dd 33 dpv ss 2 dpv dd 2 apv ss 2 vrt3 dacrefp3 atbp atbm dv dd 12 dv ss 12 shsi svsi cri7 cri6 cri5 cri4 cri3 cri2 cri1 cri0 hs2i vs2i ck2i fld2i dv dd 12 dv ss 12 dv dd 33 dv ss 33 clpp clpy1 dtbo0 dtbo1 dtbo2 clpcb2 clpcb1 dtbo3 clpcr2 clpcr1 clpy2 osdho osdvo osdcko dvdd33 dvss33 osdg osdb osdr osden osdal aic k aid a aics sd a scl dv dd 12 dv ss 12 i 2 csel xtal1 scanmd scanen xtal2 test0 test1 dpv ss 1 dpv dd 1 apv ss 1 apv dd 1 apv dd 2 dv dd 33 dv ss 33 ck1i vs1i fld1i ygi7 ygi6 ygi5 ygi4 ygi3 ygi2 ygi1 ygi0 dv dd 12 dv ss 12 cbi7 cbi6 cbi5 cbi4 cbi3 cbi2 cbi1 cbi0 apv dd 0 chpm p do apv ss 0 av dd 33_0 ayin2 av ss 33_0 ayin1 vrb0 dacrefm0 vrt0 dacrefp0 acbin2 av dd 33_1 acbin1 av ss 33_1 ascin vrb1 dacrefm1 vrt1 dacrefp1 svo atbi0 guard asyin av dd 33_2 acvbs1 av ss 33_2 acvbs2 vrb2 dacrefm2 vrt2 dacrefp2 acrin2 av dd 33_3 acrin1 av ss 33_3 vrb3 dacrefm3 nc nc nc hs1i ve1i he1i sddq16 sddq17 sddq18 sddq19 dv ss 33 dv dd 33 sddq20 sddq21 sddq22 sddq23 sddq24 sddq25 dv ss 33 dv dd 33 dv ss 12 dv dd 12 sddq26 sddq27 sddq28 sddq29 sddq30 sddq31 dv ss 33 dv dd 33 sddqm3 sddqm2 sdad3 sdad4 sdad5 sdad6 sdad7 sdad8 sdad9 dvss33 dvdd33 sdad2 sdad1 sdad0 sdad10 sdbs1 sdbs0 sdad11 sdras sdcas sdwe dvss12 sdcki dv dd 12 dv ss 33 sdcko dvdd33 sddqm1 sddqm0 sddq8 sddq9 sddq10 sddq11 dv ss 33 dv dd 33 sddq12 sddq13 193 195 200 205 210 215 220 225 230 235 240 245 250 255 256 192 190 185 180 175 170 165 160 155 150 145 140 135 130 129 1 5 10 15 20 25 30 35 40 45 50 55 60 64 128 125 120 115 110 105 100 95 90 85 80 75 70 65 LC749460W top view
LC749460W no.a1187-9/20 pin functions in/output format pin no. pin symbol i/o format connecting destination remarks 1 vrt3 i i adc3 reference power supply input 2 dacrefp3 o i adc3 reference power supply output 3 atbp i i open adc atb (analog test bus) analog input + terminal 4 atbm i i open adc atb (analog test bus) analog input - terminal 5 dv dd 12 p power supply digital 1.2v system power supply 6 dv ss 12 p gnd digital 1.2v system gnd 7 shsi i c external horizontal sync signal input 8 svsi i d external vertical sync signal input 9 cri7 i 10 cri6 i 11 cri5 i 12 cri4 i 13 cri3 i 14 cri2 i 15 cri1 i 16 cri0 i c cr/r signal input 17 hs2i i c horizontal sync signal input terminal for d2 input 18 vs2i i c vertical sync signal input terminal for d2 input 19 ck2i i a clock input terminal for d2 input 20 fld2i i c field signal input terminal for d2 input 21 dv dd 12 p power supply digital 1.2v power supply 22 dv ss 12 p gnd digital 1.2v gnd 23 dv dd 33 p power supply digital 3.3v power supply 24 dv ss 33 p gnd digital 3.3v gnd 25 clpp o e clamp pulse output terminal 26 clpy1 o clamp control terminal 27 dtbo0 o open 28 dtbo1 o open 29 dtbo2 o open digital test output terminal 30 clpcb2 o 31 clpcb1 o clamp control terminal 32 dtbo3 o open digital test output terminal 33 clpcr2 o 34 clpcr1 o 35 clpy2 o f clamp control terminal 36 osdho o external osd hsync signal output terminal 37 osdvo o external osd vsync signal output terminal 38 osdcko o e external osd output pixel clock 39 dv dd 33 p power supply digital 3.3v system power supply 40 dv ss 33 p gnd digital 3.3v system gnd 41 osdg i g signal input for osd 42 osdb i b signal input for osd 43 osdr i r signal input for osd 44 osden i osd input enable 45 osdal i c osd blending enable 46 aick i d 3-wire bus clock terminal 47 aida b h 3-wire bus data input/output terminal 48 aics i d 3-wire bus chip select terminal 49 sda b h i 2 c bus i 2 c bus data input/output terminal 50 scl i d i 2 c bus clock terminal 51 dv dd 12 p power supply digital 1.2v system power supply continued on next page.
LC749460W no.a1187-10/20 continued from preceding page. in/output format pin no. pin symbol i/o format connecting destination remarks 52 dv ss 12 p gnd digital 1.2v system gnd 53 i 2 csel i d i 2 c bus slave address selection input 54 xtal1 i a xtal (for pll1) input terminal 55 scanmd i d 56 scanen i d open test terminal 57 xtal2 i a xtal (for pll2) input terminal 58 test0 i 59 test1 i d open test terminal 60 dpv ss 1 p gnd digital gnd for pll1 61 dpv dd 1 p power supply digital 1.2v system power supply for pll1 62 apv ss 1 p gnd analog gnd for pll1 63 apv dd 1 p power supply analog 3.3v system power supply for pll1 64 apv dd 2 p power supply analog 3.3v system power supply for pll2 65 apv ss 2 p gnd analog gnd for pll2 66 dpv dd 2 p power supply digital 1.2v system power supply for pll2 67 dpv ss 2 p gnd digital gnd for pll2 68 dv dd 33 p power supply digital 3.3v system power supply 69 dv ss 33 p gnd digital 3.3v system gnd 70 xrst i b initial circuit system reset terminal (?l? reset) 71 ygo9 o 72 ygo8 o 73 ygo7 o 74 ygo6 o 75 ygo5 o 76 ygo4 o 77 ygo3 o 78 ygo2 o 79 ygo1 o 80 ygo0 o e digital g signal output terminal 81 cbo9 o 82 cbo8 o e digital b signal output terminal 83 dv dd 12 p power supply digital 1.2v system power supply 84 dv ss 12 p gnd digital 1.2v system gnd 85 dv dd 33 p power supply digital 3.3v system power supply 86 dv dd 33 p gnd digital 3.3v system gnd 87 cbo7 o 88 cbo6 o 89 cbo5 o 90 cbo4 o 91 cbo3 o 92 cbo2 o 93 cbo1 o 94 cbo0 o e digital b signal output terminal 95 cro9 o 96 cro8 o 97 cro7 o 98 cro6 o 99 cro5 o e digital r signal output terminal 100 dv dd 33 p power supply digital 3.3v system power supply 101 dv ss 33 p gnd digital 3.3v system gnd 102 cro4 o 103 cro3 o 104 cro2 o e digital r signal input terminal continued on next page.
LC749460W no.a1187-11/20 continued from preceding page. in/output format terminal no. terminal symbol i/o format connection destination remarks 105 cro1 o 106 cro0 o e digital r signal input terminal 107 vso o e vertical sync signal output terminal 108 hso o e horizontal sync signal output terminal 109 cko o g pixel clock output terminal 110 deo/heo o e data enable /horizontal data enable output terminal 111 fldo/veo o e field signal/vertical data enable output terminal 112 pwmo o g pwm output terminal 113 dv dd 12 p power supply digital 1.2v system power supply 114 dv ss 12 p gnd digital 1.2v system gnd 115 dv dd 33 p power supply digital 3.3v system power supply 116 dv ss 33 p gnd digital 3.3v system gnd 117 sddq0 b 118 sddq1 b 119 sddq2 b 120 sddq3 b 121 sddq4 b 122 sddq5 b h sdram sdram data input/output terminal 123 dv dd 33 p power supply digital 3.3v system power supply 124 dv ss 33 p gnd digital 3.3v system gnd 125 sddq6 b 126 sddq7 b 127 sddq15 b 128 sddq14 b 129 sddq13 b 130 sddq12 b h sdram sdram data input/output terminal 131 dv dd 33 p power supply digital 3.3v system power supply 132 dv ss 33 p gnd digital 3.3v system gnd 133 sddq11 b 134 sddq10 b 135 sddq9 b 136 sddq8 b h sdram sdram data input/output terminal 137 sddqm0 o sdram dqm0 output terminal 138 sddqm1 o g sdram sdram dqm1 output terminal 139 dv dd 33 p power supply digital 3.3v system power supply 140 sdcko o g sdram sdram clock output terminal 141 dv ss 33 p gnd digital 3.3v system gnd 142 dv dd 12 p power supply digital 1.2v system power supply 143 sdcki i a sdram sdram clock input terminal 144 dv ss 12 p gnd digital 1.2v system gnd 145 sdwe o sdram write enable output terminal 146 sdcas o sdram column address strobe output terminal 147 sdras o g sdram sdram low address strobe output terminal 148 sdad11 o g sdram sdram address output terminal 149 sdbs0 o sdram bank 0 selection output terminal 150 sdbs1 o g sdram sdram bank 1 selection output terminal 151 sdad10 o 152 sdad0 o 153 sdad1 o 154 sdad2 o g sdram sdram address output terminal 155 dv dd 33 p power supply digital 3.3v system power supply 156 dv ss 33 p gnd digital 3.3v system gnd 157 sdad9 o 158 sdad8 o g sdram sdram address output terminal continued on next page
LC749460W no.a1187-12/20 continued from preceding page. in/output format terminal no. terminal symbol i/o format connection destination remarks 159 sdad7 o 160 sdad6 o 161 sdad5 o 162 sdad4 o 163 sdad3 o g sdram sdram address output terminal 164 sddqm2 o sdram dqm2 output terminal 165 sddqm3 o g sdram sdram dqm3 output terminal 166 dv dd 33 p power supply digital 3.3v system power supply 167 dv ss 33 p gnd digital 3.3v system gnd 168 sddq31 b 169 sddq30 b 170 sddq29 b 171 sddq28 b 172 sddq27 b 173 sddq26 b h sdram sdram data input/output terminal 174 dv dd 12 p power supply digital 1.2v system power supply 175 dv ss 12 p gnd digital 1.2v system gnd 176 dv dd 33 p power supply digital 3.3v system power supply 177 dv ss 33 p gnd digital 3.3v system gnd 178 sddq25 b 179 sddq24 b 180 sddq23 b 181 sddq22 b 182 sddq21 b 183 sddq20 b h sdram sdram data input/output terminal 184 dv dd 33 p power supply digital 3.3v system power supply 185 dv ss 33 p gnd digital 3.3v system gnd 186 sddq19 b 187 sddq18 b 188 sddq17 b 189 sddq16 b h sdram sdram data input/output terminal 190 he1i i c horizontal data enable signal input terminal for digital input 1 191 ve1i i c vertical data enable signal input terminal for digital input 1 192 hs1i i c horizontal sync signal input terminal for digital input 1 193 dv dd 33 p power supply digital 3.3v system power supply 194 dv ss 33 p gnd digital 3.3v system gnd 195 ck1i i a pixel clock input terminal for digital input 1 196 vs1i i c vertical sync signal input terminal for digital input 1 197 fld1i i c field discrimination signal input terminal for digital input 1 198 ygi7 i 199 ygi6 i 200 ygi5 i 201 ygi4 i 202 ygi3 i 203 ygi2 i 204 ygi1 i 205 ygi0 i c sy/y/g signal input 206 dv dd 12 p power supply 1.2v system power supply 207 dv ss 12 p gnd 1.2v system gnd 208 cbi7 i 209 cbi6 i 210 cbi5 i c c/cb/b signal input continued on next page
LC749460W no.a1187-13/20 continued from preceding page. in/output format terminal no. terminal symbol i/o format connection destination remark 211 cbi4 i 212 cbi3 i 213 cbi2 i 214 cbi1 i 215 cbi0 i c c/cb/b signal input 216 apv dd 0 p power supply analog power supply for pll0 217 chpmpdo o i charge pump output 218 apv ss 0 p gnd analog gnd for pll0 219 av dd 33_0 p power supply analog 3.3v system power supply for adc0 220 ayin2 i i analog i/f analog y2 signal input 221 av ss 33_0 p gnd analog 3.3v system gnd for adc0 222 ayin1 i i analog i/f analog y1 signal input 223 vrb0 i i adc0 reference power supply output 224 dacrefm0 o i adc0 reference power supply output 225 vrt0 i i adc0 reference power supply output 226 dacrefp0 o i adc0 reference power supply output 227 acbin2 i i analog i/f analog cb2 signal input 228 av dd 33_1 p power supply analog 3.3v system power supply for adc1 229 acbin1 i i analog i/f analog cb1 signal input 230 av ss 33_1 p gnd analog 3.3v system gnd for adc1 231 ascin i i analog i/f analog sc signal input 232 vrb1 i i adc1 reference power supply input 233 dacrefm1 o i adc1 reference power supply output 234 vrt1 i i adc1 reference power supply input 235 dacrefp1 o i adc1 reference power supply output 236 svo o i analog i/f analog signal input 237 atbi0 i i open analog test input terminal 238 guard i i gnd analog guard band terminal 239 asyin i i analog i/f analog sy signal input 240 av dd 33_2 p power supply analog 3.3v system power supply for adc2 241 acvbs1 i i analog i/f analog cvbs1 signal input 242 av ss 33_2 p gnd analog 3.3v system gnd for adc2 243 acvbs2 i i analog i/f analog cvbs2 signal input 244 vrb2 i i adc2 reference power supply input 245 dacrefm2 o i adc2 reference power supply output 246 vrt2 i i adc2 reference power supply input 247 dacrefp2 o i adc2 reference power supply output 248 acrin2 i i analog i/f analog cr2 signal input 249 av dd 33_3 p power supply analog 3.3v system power supply for adc3 250 acrin1 i i analog i/f analog cr1 signal input 251 av ss 33_3 p gnd analog 3.3v system gnd for adc3 252 vrb3 i i adc3 reference power supply input 253 dacrefm3 o i adc3 reference power supply output 254 nc 255 nc 256 nc
LC749460W no.a1187-14/20 pin type in/output form function equival ent circuit application terminal a 5v tolerant input ck1i, ck 2i, xtal1, xtal2, sdcki, b 5v tolerant schmitt trigger input xrst c 5v tolerant with pulldown input ygi0 to 7, cbi0 to 7, cri0 to 7, he1i, ve1i, hs1i, vs1i, fld1i, hs2i, vs2i, fld2i, shsi, osdg, osdb, osdr, osden, osdal d 5v tolerant with pull down schmitt trigger input svsi, aick, aics, scl, i2csel, scanmd, scanen (*no use open), test0, test1 e 8ma 3-state drive input ygo0 to 9, cbo0 to 9, cro0 to 9 vso, hso, deo/he o, fldo/veo, clpp, osdho, osdvo, osdcko f 8ma 3-state drive input dtbo0 to 3, clpy1 clpcb1, clpcr1, clpy2 clpcb2, clpcr2 g 12ma 3-state drive input cko, sdcko, pwmo, sdras, sdcas, sdwe, sdad0 to 11, sdbs0 to 1, sddqm0 to 3 h 5v tolerant 12ma 3-state drive input/output aida, sda, sddq0 to 31 i analog input/output vrt0 to 3, vrb0 to 3, dacrefp0 to 3, dacrefm0 to 3, atbp, atbm, chpmpdo, svo, guard, acvbs1, acvbs2, asyin, ascin, ayin1, ayin2, acbin1, acbin2, acrin1, acrin2, atbi0
LC749460W no.a1187-15/20 electrical characteristics absolute maximum ratings v ss = 0v parameter symbol rating unit max supply voltage (i/o) dv dd 33 av dd 33 -0.3 to +3.96 v max supply voltage (core) dv dd 12 av dd 12 -0.3 to +1.44 v input voltage v i -0.5 to 6.0 v output voltage v o -0.3 to v dd +0.3 v storage temperature tstg -55 to +125 c operating temperature topr -30 to +70 c max supply current pd max tdb w allowable operation range at ta = -30 to +70 c parameter symbol min typ max unit supply voltage (i/o) dv dd 33 3.15 3.3 3.45 v supply voltage (core) v dd 12 1.08 1.2 1.32 v supply voltage (analog) av dd 33 3.15 3.3 3.45 v supply voltage (pll) apv dd 3.15 3.3 3.45 v input voltage range v in 05.5 v i/o terminal capacitance at ta = 25 c , v dd = v i = 0v parameter symbol conditions min typ max unit input terminal cin f=1mhz 10 pf output terminal cout f=1mhz 10 pf i/o terminal ci/o f=1mhz 10 pf dc characteristics at ta = -30 to +70 c, v dd 33 = 3.15 to 3.45v, v dd 12 = 1.08v to 1.32v parameter symbol conditions min typ max unit input with 5v tolerant 2.0 5.5 v input high-level voltage v ih schmitt input with 5v tolerant 2.0 5.5 v input with 5v tolerant -0.3 +0.8 v input low-level voltage v il schmitt input with 5v tolerant -0.3 +0.8 v v i =v dd -10 +10 a input high-level current i ih v i =v dd , with pull-down resistance +10 +100 a input low-level current i il v i =v ss -10 +10 a output high-level voltage v oh cmos 2.4 v output low-level voltage v ol cmos 0.4 v output leak current ioz at output of high-impedance -10 +10 a pull-down resistor rdn 50 97 272 k dynamic supply current iddop t ck =85mhz tbd ma static supply current *1 iddst output release, v i =v ss or v dd tbd a * 1: there is a input terminal which builds in pull down resist ance. please note that there is no guarantee about static consumption current depending on circuit composition.
LC749460W no.a1187-16/20 a/d convertor characteristics at ta = -30 to +70 c, dv ss = 0v, av ss = 0v electric characteristic parameter symbol conditions min typ max unit sampling frequency fclk 10 80 mhz clamp pulse width tcl 0.45 s analog input coupling capacitor cal 0.1 f analog input frequency fal 30 mhz analog input amplitude val 1.0 vp-p svo amplifier bandwidth fsvo 5mhz svo amplifier output load capacitor csvo 20 pf external between dacrefp/dacrefm capacitor cext 0.08 0.1 1 f adc characteristics parameter symbol conditions min typ max unit resolution nob 10 bits *1 8 bits enob enob *2 7.5 bits *1 0.5 lsb derivative linearity error dnl *2 0.5 lsb *1 2 lsb integral linearity error inl *2 2 lsb operation power current 3.3v power i dd 3 *2, *3 60 ma 1.2v power i dd *2, *3 1.5 ma standby power current 3.3v power i sb 3 *3 -10 +10 a 1.2v power i sb *3 -10 +10 a * 1 v dd 3=3.3v, fclk=27mhz, fin=100khz * 2 v dd 3=3.3v, fclk=80mhz, fin=100khz * 3 it describes value per 1ch note: adc cannot standby. apply a square wave with a constant frequency when adc is not to be used. i/o data timing (1) input data timing 1 pin name parameter symbol min max unit clock l-level time t lo 6.25 ns clock h-level time t hi 6.25 ns ck1i, ck2i clock cycle t ck 12.5 ns input data setup time t su 2 ns ygi [7:0], cbi [7:0], cri [7:0], he1i, ve1i, hs1i, vs1i, fld1i, hs2i, vs2i, fld2i input data hold time t hd 1 ns * the recommended duty cycle of input clock is 50% t hi t lo t ck t su t hd clk in p ut data v dd 33/2 v dd 33/2
LC749460W no.a1187-17/20 (2) input data timing 2 pin name parameter symbol min max unit clock l-level time t lo 3.00 ns clock h-level time t hi 3.00 ns sdcki clock cycle t ck 6.00 ns input data setup time t su 2 ns sddq [31:0] input data hold time t hd 1 ns (3) output data timing 1 pin name parameter symbol min max unit clock l-level time t lo 5.88 ns clock h-level time t hi 5.88 ns cko clock cycle t ck 11.76 ns output data delay time t ac -1.5 +1.5 ns ygo [9:0], cbo [9:0], cro [9:0], vso, hso, deo/heo, fldo/veo, osdho, osdvo, osdcko output data hold time t hd 9.00 ns (4) output data timing 2 pin name parameter symbol min max unit clock l-level time t lo 3.00 ns clock h-level time t hi 3.00 ns sdcko clock cycle t ck 6.00 ns output data delay time t ac -1.0 +1.0 ns sdras, sdcas, sdwe, sdad [11:0], sdbs [1:0], sddqm [3:0] output data hold time t hd 4 ns t hi t lo t ck t su t hd sdcki in p ut data v dd 33/2 v dd 33/2 t hi t lo t ck t ac t hd sdcko output data v dd 33/2 v dd 33/2 t hi t lo t ck t ac t hd cko output data v dd 33/2 v dd 33/2
LC749460W no.a1187-18/20 (5) output data timing 3 pin name parameter symbol min max unit clock l-level time t lo 5.88 ns clock h-level time t hi 5.88 ns osdcko clock cycle t ck 11.76 ns output data delay time t ac -1.5 +1.5 ns osdho, osdvo, osdcko output data hold time t hd 9.00 ns t hi t lo t ck t ac t hd osdcko output data v dd 33/2 v dd 33/2
LC749460W no.a1187-19/20 block diagram itu-r bt656 (8bits) cvbs, y-c, ycbcr, ypbpr satellite/terrestrial (digital 16bits) i2c bus clk lcd panel (wxga) LC749460W 64mbit sdram (512kword 32bit 4banks) or 128mbit sdram (1024kword 32bit 4banks) pll i2c lvds tx memory i/f ext. osd 8 16 osd de- interlacer motiondet. film mode crosscolor luminance cancel picture quality improvement white/black stretch fti brightness contrast pop pip scaler s w 3d-nr video decoder 4ch 10bit adcs & afe 3wire bus 3wire bus gamma dithering
LC749460W no.a1187-20/20 application circuit example ps sub video decoder tuner cvbs micro-controller y/cb/cr LC749460W wxga lcd-panel lvds tx y/c y c y cb cr adc ch2 sw video decoder de-interlacer scaler pop/pip picture improve cb c r y adc ch1 sw adc ch3 sw adc ch0 8 cvbs cvbs lv78200 sync sep hs/vs mpeg2 decoder 16 sdram y/cb/cr this catalog provides informati on as of june, 2008. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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